1. Field of the Invention
This application relates to the general field of computer aided design of monolithic three-dimensional integrated circuits.
2. Discussion of Background Art
Use of computer programs for automating the design of electronic circuits, and particularly for assisting in the design of semiconductor integrated circuits, has been known for at least forty years. This field of Computer-Aided Design (CAD) encompasses the spectrum of engineering activities from early capture of the design idea, through its various refinements (both automatic and manual), modeling, simulations, down to its mapping to physical objects, partitioning and floor-planning, placement and routing, rule-checking and mask-making. The first part of these activities occurs in the logical domain, before mapping to physical objects (macros and cells) occurs, and is known as logic design. The part of the process after mapping the logical design to physical objects is known as physical design.
The rapid shrinking of manufacturable transistor dimensions on semiconductor wafers gave rise to a corresponding explosion of the design sizes that CAD tools need to handle. Modern designs routinely exceed tens and hundreds of millions of transistors and require massive and elaborate CAD tools to handle them.
A typical physical design process is illustrated in FIG. 1. It may start with a netlist 105 made of physical objects, and a set of constraints 110 derived from the logical part of the design flow. Netlist 105 with constraints 110 may be partitioned into a small set of blocks, on the order of 1 to 100 using a program called partitioner 115, which may produce a modified partitioned netlist 135 and modified netlist constraints 140. These, in turn, may be fed into a floor-planner 145 that may arrange these blocks mosaic-like, while respecting design netlist constraints 140, on a rectangular frame that may outline the physical footprint of the final integrated circuit (IC) and produce a newly modified netlist 155 and newly modified design constraints 160. The objects within each floor-planned block of newly modified netlist 155 may then be assigned a location within that block, while respecting newly modified design constraints 160, using the placer 165. Following this step the placed design netlist 175 and modified design constraints 180 may be passed to other CAD tools that may perform routing utilizing router 185, and producing routed netlist 190 that may be passed downstream for rule checking and further processing 195 for the final IC manufacturing. Throughout the CAD process the various CAD tools may use, in addition to the design itself and its constraints, a variety of libraries that describe the netlist objects in their various abstractions, and rules files that define the permissible actions on objects and legal relations between them, and between objects and an abstraction of the underlying technology layers. Further, user intervention may be required at the various steps above.
Traditionally CAD tools operate with the understanding that the underlying transistors are arranged in a single planar layer. In recent years some tools have expanded to consider transistors arranged on multiple stacked layers, where the layers may be connected through relatively large Through-Silicon Vias (TSV) such as described in Xie, Y., Cong, J., Sapatnekar, S. “Three-Dimensional Integrated Circuit Design,” Springer, 2010. The focus of this expansion, however, is benefiting from the three-dimensional stacking while minimizing the use of the very large and expensive TSVs.